The biggest advantage of such a circuit is its high speed. As shown in the figure above, the CC signal is connected to the start conversion input in order to convert the cycle continuously. As the SAR determines each bit, digital data is also available serially. The CC signal in turn enables the latch, and digital data appear at the output of the latch. After Q0 is tried, the SAR makes the conversion complete (CC) signal HIGH to show that the parallel output lines contain valid data. This process goes on until all the bits are tried. If comparator output is HIGH, D/A output will be less than V in and the MSB will be set to the next position (Q7 to Q6) by the SAR.Īccording to the comparator output, the SAR will either keep or reset the Q6 bit. If comparator output is LOW, D/A output will be greater than V in and the MSB will be cleared by the SAR. The output is given to the D/A converter which produces an analog equivalent of the MSB and is compared with the analog input V in. The MSB of the SAR (Q7) is set as soon as the first transition from LOW to HIGH is introduced. This prevents signals with frequencies greater than the sampling rate from being seen by the ADC, causing a detrimental effect called aliasing. The 8-bit latch at the end of conversation holds onto the resultant digital data output.Īt the start of a conversion cycle, the SAR is reset by making the start signal (S) high. Analog-to-digital converter circuits (ADC) are usually equipped with analog low-pass filters to pre-condition the signal prior to digitization.
Till the digital output (8 bits) of the SAR is equivalent to the analog input V in, the SAR adjusts itself.
Analog to digital converter circuits serial#
The output of the comparator is a serial data input to the SAR. The analog output V a of the D/A converter is then compared to an analog signal V in by the comparator. The main part of the circuit is the 8-bit SAR, whose output is given to an 8-bit D/A converter. Successive Approximation Type Analog to Digital Converter